Hardcore ARM/XScale Cache Control
Posted: Oct 24, 2003 @ 10:30amHi folks.
I wonder if anyone has ever successfully changed the cache control of ARM / XScale CPU's.
Especially the XScale streaming cache looks nice. It would be a perfect canditate to speed up sound mixing and rendering functions.
I'm writing for WinCE, so I think I need to hack myself into the memory management.. Or is there a simpler way?
What I found out so far is, that I need to create a new descriptor that maps the process memory to a different virtual address. There are two bits inside the descriptor that do the cache control. That way I could access the same physical memory using the different caches. I just haven't figured out how I can create such a descriptor (or where the descriptor table is at all)
I've seen crazy dma-transfers codes and other low-level stuff here, so I hope there are some lowlevel freaks on this board.
I wonder if anyone has ever successfully changed the cache control of ARM / XScale CPU's.
Especially the XScale streaming cache looks nice. It would be a perfect canditate to speed up sound mixing and rendering functions.
I'm writing for WinCE, so I think I need to hack myself into the memory management.. Or is there a simpler way?
What I found out so far is, that I need to create a new descriptor that maps the process memory to a different virtual address. There are two bits inside the descriptor that do the cache control. That way I could access the same physical memory using the different caches. I just haven't figured out how I can create such a descriptor (or where the descriptor table is at all)
I've seen crazy dma-transfers codes and other low-level stuff here, so I hope there are some lowlevel freaks on this board.