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ASM and immediate values

PostPosted: Mar 4, 2004 @ 8:50pm
by fast_rx

PostPosted: Mar 4, 2004 @ 10:13pm
by StephC
There is no single instruction which will load a 32 bit immediate constant
into a register without performing a data load from memory.

• All ARM instructions are 32 bits long
• ARM instructions do not use the instruction stream as data.

The data processing instruction format has 12 bits available for
operand2

• If used directly this would only give a range of 4096.

Instead it is used to store 8 bit constants, giving a range of 0 - 255.
These 8 bits can then be rotated right through an even number of
positions (ie RORs by 0, 2, 4,..30).

• This gives a much larger range of constants that can be directly loaded,
though some constants will still need to be loaded
from memory.

This gives us:

• 0 - 255 [0 - 0xff]
• 256,260,264,..,1020 [0x100-0x3fc, step 4, 0x40-0xff ror 30]
• 1024,1040,1056,..,4080 [0x400-0xff0, step 16, 0x40-0xff ror 28]
• 4096,4160, 4224,..,16320 [0x1000-0x3fc0, step 64, 0x40-0xff ror 26]

These can be loaded using, for example:

• MOV r0, #0x40, 26 ; => MOV r0, #0x1000 (ie 4096)

To make this easier, the assembler will convert to this form for us if
simply given the required constant:

• MOV r0, #4096 ; => MOV r0, #0x1000 (ie 0x40 ror 26)

The bitwise complements can also be formed using MVN:

• MOV r0, #0xFFFFFFFF ; assembles to MVN r0, #0

If the required constant cannot be generated, an error will
be reported.

Loading full 32 bit constants

Although the MOV/MVN mechansim will load a large range of constants
into a register, sometimes this mechansim will not generate the required
constant.

Therefore, the assembler also provides a method which will load ANY 32
bit constant:


• LDR rd,=numeric constant

If the constant can be constructed using either a MOV or MVN then this
will be the instruction actually generated.

Otherwise, the assembler will produce an LDR instruction with a PC relative address to read the constant from a literal pool.

• LDR r0,=0x42 ; generates MOV r0,#0x42
• LDR r0,=0x55555555 ; generate LDR r0,[pc, offset to lit pool]

As this mechanism will always generate the best instruction for a given
case, it is the recommended way of loading constants.

PostPosted: Mar 4, 2004 @ 10:38pm
by refractor

PostPosted: Mar 4, 2004 @ 10:42pm
by StephC

PostPosted: Mar 4, 2004 @ 10:43pm
by Kzinti

PostPosted: Mar 5, 2004 @ 4:13am
by fast_rx