StrongARM instruction set and opcode list

[jont]

[refractor]

I believe it'll a coprocessor instruction on the StrongARM (co-pro 15 is the only one implemented too I think).

You might have to try and force the processor into supervisor mode to access the "coprocessor", and I'm not entirely sure PocketPC2002 will let you do that. It's definitely worth a try though, because I've been doing some low-level stuff and it hasn't complained at all so far to me (though I've not tried changing modes).

You want to look at the MRS and MSR instructions - move the current processor status register (CPSR) into a general purpose register, clear the bottom 5 bits, set it to 11001 (supervisor mode) and shove it back into the CPSR (using the copro, IIRC) and see what happens. I can post more detailed code to do that tomorrow if you need it (though I'd just cut and paste from an interrupt service routine, so you might have better luck elsewhere or trying it out yourself)....

Hope that helps,

Ref.

[refractor]

(Sorry, I should've said, I would think that any cache-flushing routines are buried somewhere in the vendor-specific part of the kernel and would be hard to find and pretty inaccessible/inhospitable to user routines).

[Digby]

[refractor]

[jont]

[Guest]

lea is load effective address. It's used mostly to add two or more operands to create an effective address. Stack vars, for instance, usually are relative ebp, so lea ebx,[ebp+4] adds 4 to ebp and returns the result in ebx. You can also use a scale (+4 would be index of ebp) such as lea ebx,[ebp+esi*4]. This instruction is also used as a fast multiplier, for a limited set of multipliers (can also add in an index to get x5, etc.). mov ebx, offset * works the same as a simple lea ebx, offset, but mov won't do for stack vars, and it doesn't index, and it doesn't scale, and none of this is in an ARM.

[deax]

[jont]

Anon: Thanks for the reply.
I'm aware that lea is nothing to do with ARM (I did tons of x86 asm in the old days but years of self-abuse have erased the important bits), but thought an ARM assembly thread might attract some x86 types
So if I restrict myself to 286 instructions in real mode then I can pretty much assume that "lea reg16,[adr]" is the same as "mov reg16,number" ?
Cheers

[Digby]

You can call CacheSync from an app. I use it to flush the data cache each time I run a series of my memory bandwidth benchmarks.

[jont]

Digby

Sorry to sound like an idiot, but will I need Platform Builder SDK to access the CacheSync function? I don't appear to have pkfuncs in any of my include directories, or anywhere else on my HDD for that matter.

Cheers

[refractor]

You'll need the pkfuncs.h file from somewhere, yes...

[jont]

Time to go rooting through the yellow CDs in MSDN library then I guess working for a software dev company has some benefits ...