by Orpe » Mar 1, 2002 @ 2:33am
Since there's no API for detecting when the refresh starts it's probably hard to use what I just tried, but it works for iPAQs (at least for the 3660 that I've tested on so far).
On this model (and probably most of the others) the LCD controller which comes "built in" with the processor is used. It uses DMA to transfer data from the internal DRAM buffer to a small internal buffer (something like 5 DWORDS in size). This data is then used to drive the display. So, basically it does many short DMA transfers and the start address of these transfers can be read from a memory mapped register. (This requires some tinkering).
But, by reading this register you will know the approximate line it's currently refreshing and when this counter wraps around, you know that the refresh restarts at the top of the screen.
The time it takes for a wraparound to occur (approx 16687 microseconds) on my device indicates that the refresh rate is probably 60Hz (if you do the computation based on that single number you get 59.92Hz).
However, I'm not sure that having the vsync helps anything when it comes to vertical tearing (as you get from rotating blits). On a CRT there is actually a pause after the last line has been refreshed during which the ray is moved back up to the top again. This probably isn't the case on LCDs, they may just start at the top again straight away... but I don't really know how they work.
OTOH, when you're playing around with hardware registers like this, you may as well do things properly. It's actually possible to change the location from where the LCD controller reads data which means that the blit can be removed altogether. I haven't tried this yet but I probably will tomorrow. It doesn't seem very difficult. In this case you can do a rotating blit to a backbuffer and then switch/flip to this backbuffer by changing where the LCD reads data from.
/Orpe